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CXG1081TN
Receiving Dual-Band Mixer
Description The CXG1081TN is a receiving dual-band mixer MMIC. This IC is designed using the Sony's GaAs JFET process. Features * High conversion gain Gc = 9.5 to 10.0dB (Typ.) * Low noise figure NF = 4.6 to 4.7dB (Typ.) * Single 2.7V power supply operation * Low LO input power operation PLO = -15dBm * Single CTL pin achieved by the built-in inverter circuit * 10-pin small package Applications 800MHz Japan digital cellular telephones (PDC) Structure GaAs J-FET MMIC 16 pin TSSOP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 4.5 V * Input power PIN +5 dBm * Current consumption IDD (Mixer block) 15 mA * Operating temperature Topr -35 to +85 C * Storage temperature Tstg -65 to +150 C Recommended Operating Conditions * Supply voltage VDD 2.7 to 3.3 * Control voltage VCTL (H) VCTL (L) 2.4 to 3.3 0 to 0.3
V V V
Block Diagram
Pin Configuration
RFIN1 RFIN1 6 5 RFIN2 CTL GND VDD1 (LO AMP1)
6 7 8 9
5 4 3 2 1
RFIN2 OPT GND VDD2 (LO AMP2) LO IN
IF OUT/VDD3 (MIX) 10
IF OUT 10
1 LO IN
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99654A9Z-PS
CXG1081TN
Electrical Characteristics Conditions: VDD = 2.7V, VCTL (H) = 2.7V, VCTL (L) = 0V, fRF1 = 870MHz, fRF2 = 820MHz, fLO = fRF - 130MHz, PLO = -15dBm, unless otherwise specified (Ta = 25C) Item Current consumption Control current Symbol IDD Path VDD1, VDD2 VDD3 GND CTL GND CTL GND RFIN1 IFOUT Conversion gain GC RFIN2 IFOUT RFIN1 IFOUT RFIN2 IFOUT RFIN1 IFOUT Input IP3 IIP3 RFIN2 IFOUT LO to RF leak level PLK LOIN RFIN1 LOIN RFIN2 L H L 0.5 -- -- 3 -29 -29 -- -23 -23 VCTL H L H L H L H L H L H Min. -- -- -1 8 -- -- 8 -- -- 0 Typ. 5.7 35 0 9.5 -17 -19 10 4.6 4.7 -2.5 Max. 7.3 70 -- 11.5 -12 -14 11.5 6.5 6.5 -- dB PRF = -25dBm, offset = 100kHz dBm Conversion by the IM3 suppression ratio for two-wave input dBm fLO = 740MHz fLO = 690MHz dB When a small signal Unit mA When no signal A Measurement condition
ICTL
Noise figure
NF
Note) The values shown above are the specified values on the Sony's recommended evaluation board.
-2-
CXG1081TN
Recommended Evaluation Circuit
RFIN1 50
L7
L6 6 L8 5
L9
L10 L11
RFIN2 50
R1 7 CTL 8 VDD1 (LO AMP1) C5 IF OUT 50 C2 L2 C3 VDD3 (MIX) L4 9 C4 L1 10 C1 1 50 L3 2 C6 C7 LO IN 3 L5 VDD2 (LO AMP2) 4
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10
120nH 82nH 27nH 33nH 39nH 27nH 15nH 18nH 33nH 8.2nH
L11 C1 C2 C3 C4 C5 C6 C7 R1
15nH 6pF 1000pF 1000pF 100pF 1000pF 100pF 1000pF 470
-3-
CXG1081TN
Example of Representative Characteristics (Ta = 25C)
Path RFIN1 IFOUT GC, NF vs. fRF
12 Gc - Conversion gain, NF - Noise figure [dB] VDD = 2.7V VCTL = 2.7V fLO = fRF - 130MHz PLO = -15dBm GC 8 Gc - Conversion gain, NF - Noise figure [dB] 12 VDD = 2.7V VCTL = 0V fLO = fRF - 130MHz PLO = -15dBm
Path RFIN2 IFOUT GC, NF vs. fRF
10
10 GC 8
6 NF 4
6 NF 4
2 800
820
840
860
880
900
2 800
820
840
860
880
900
fRF - RF frequency [MHz]
fRF - RF frequency [MHz]
Path RFIN1 IFOUT POUT, IM3 vs. PIN
20 10 POUT - IF output power [dBm] POUT -10 -20 -30 -40 IM3 -50 -60 -70 -80 -40 -30 -20 -10 0 10 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = -15dBm POUT - IF output power [dBm] 0 20 10 0
Path RFIN2 IFOUT POUT , IM3 vs. PIN
POUT -10 -20 -30 -40 IM3 -50 -60 -70 -80 -40 -30 -20 -10 0 10 VDD = 2.7V VCTL = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = -15dBm
PIN - RF input power [dBm]
PIN - RF input power [dBm]
-4-
CXG1081TN
Path RFIN1 IFOUT GC, NF vs. PLO
12 Gc - Conversion gain, NF - Noise figure [dB] Gc - Conversion gain, NF - Noise figure [dB] GC 10 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fLO = 740MHz 12
Path RFIN2 IFOUT GC, NF vs. PLO
GC 10 VDD = 2.7V VCTL = 0V fRF2 = 820MHz fLO = 690MHz
8
8
6 NF 4
6 NF
4
2 -25
-20
-15
-10
-5
0
2 -25
-20
-15
-10
-5
0
PLO - LO input power [dBm]
PLO - LO input power [dBm]
Path RFIN1 IFOUT IIP3, PLK vs. PLO
8 7 IP3 - Input IIP3 [dBm] 6 5 4 3 IIP3 2 1 -25 -37.5 -40 0 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = -15dBm -22.5 -25 PLK - LO leak power [dBm] IP3 - Input IIP3 [dBm] -27.5 -30 -32.5 -35 8 7 6
Path RFIN2 IFOUT IIP3, PLK vs. PLO
VDD = 2.7V VCTL = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = -15dBm PLK 5 4 3 IIP3 2 1 -25 -37.5 -40 0 -30 -32.5 -35 -22.5 -25 -27.5 PLK - LO leak power [dBm]
PLK
-20
-15
-10
-5
-20
-15
-10
-5
PLO - LO input power [dBm]
PLO - LO input power [dBm]
-5-
CXG1081TN
Example of Characteristics for Option Resistance R1 Changed (Ta = 25C)
IDD3 (MIX) vs. R1
10 IDD3 - Mixer block current consumption [mA] VDD = 2.7V VCTL = 2.7V or VCTL = 0V 8
6
4
2
0 OPEN 1500
820
680
560
470
270
150
R1 - Option resistance []
Path RFIN1 IFOUT GC, NF vs. R1
12 Gc - Conversion gain, NF - Noise figure [dB] Gc - Conversion gain, NF - Noise figure [dB] 12
Path RFIN2 IFOUT GC, NF vs. R1
GC 10
10 GC 8 VDD = 2.7V VCTL = 2.7V fRF = 870MHz fLO = 740MHz PLO = -15dBm NF 4
8
6
6 NF
VDD = 2.7V VCTL = 0V fRF = 820MHz fLO = 690MHz PLO = -15dBm
4
2 OPEN 1500
820
680
560
470
270
150
2 OPEN 1500
820
680
560
470
270
150
R1 - Option resistance []
R1 - Option resistance []
Path RFIN1 IFOUT IIP3, PLK vs. R1
8 VDD = 2.7V VCTL = 2.7V fRF = 870MHz fLO = 740MHz PLO = -15dBm -20 8
Path RFIN2 IFOUT IIP3, PLK vs. R1
-20 VDD = 2.7V VCTL = 0V fRF = 820MHz fLO = 690MHz PLO = -15dBm PLK
PLK - LO leak power [dBm]
4 PLK 2 IIP3 0
-28
4
-28
IIP3 2 -32
-32
-36
0
-36
-2 OPEN 1500
820
680
560
470
270
-40 150
-2 OPEN 1500
820
680
560
470
270
-40 150
R1 - Option resistance []
R1 - Option resistance []
-6-
PLK - LO leak power [dBm]
6 IP3 - Input IIP3 [dBm]
-24
6 IP3 - Input IIP3 [dBm]
-24
CXG1081TN
Recommended Evaluation Board Front
25mm
SONY CXG1081TN EVB
RFIN1 L7 L10 L8 L6 25mm C5C4 L4 C1 L1 L2 C2 IFOUT LOIN C3 L11 L9 R1 L5 C6 C7 L3 RFIN2
CTL
VDD3
GND
VDD1/2
Back
VDD1/2
GND
VDD3
CTL
Glass fabric-base 4-layer epoxy board (thickness: 0.2mm x 2), total thickness: 0.8mm GND for the whole 2nd and 3rd layers
-7-
CXG1081TN
Package Outline
Unit: mm
10PIN TSSOP(PLASTIC)
1.2MAX 2.8 0.1 10 6 0.1
2.2 0.1
+ 0.15 0.1 - 0.05
3.2 0.2
1
5 0.5 0.25 0 to 10
0.22
0.1
M
(0.2) + 0.08 0.22 - 0.07
DETAIL A
NOTE: "" Dimensions do not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-10P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02g
-8-
(0.1) + 0.025 0.12 - 0.015
A
0.45 0.15

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